A low ON-state resistance and a low switching loss are requested for a semiconductor power element besides a high withstand voltage. However, a currently prevailing primary silicon (Si) power element reaches logical performance limitations. Silicon carbide (SiC) has a dielectric breakdown electric field strength about one digit greater than Si. Therefore, element resistance can be reduced logically three digits or more by making a drift layer thin about 1/10 times for securing the withstand voltage and by increasing an impurity concentration about 100 times. In addition, an operation of SiC at a high temperature is also possible because a band gap of SiC is larger about 3 times than that of Si. Therefore, a SiC semiconductor element is expected to have excellent performance exceeding a Si semiconductor element.
By paying attention to merits of SiC, a DMOS (Double-Diffused MOSFET) is being studied and developed as a high withstand-voltage power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
Patent Document 1 (Japanese Patent Application Laid-open No. 2016-9852) discloses an example of a method of manufacturing the DMOS. Here, described are an element region 1A positioned in a center portion of a semiconductor chip, and a termination region 1B disposed on a peripheral portion of the semiconductor chip so as to surround the element region 1A.